View LV25450PNW_5646045.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

orderin g numbe r : ena1668 bi-cmos lsi for automotive applications dsp tuner front end LV25450PNW overview the LV25450PNW is a tuner front end ic that supports the sanyo sdrs500 car radio dsp. the LV25450PNW supports worldwide radio standards including the fm bands used in us, europe, east-europe, and japan as well as the lw, mw, sw, and fm weather bands. it adopts an image canceling mixer for the fm mixer and incorporates a fast pll locking function. the LV25450PNW also supports automatic alignment using ccb bus control. it requires external eeprom. the LV25450PNW can implement a dsp tuner at low co st with a minimal number of external components. functions ? am,/fm-fe, if, and pll circuits ? ccb is a registered trademark of sanyo electric co., ltd. ? ccb is sanyo semiconductor's original bus format. all bus addresses are managed by sanyo semiconductor for this format. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 31010 sy 20081121-s00006 no.a1668-1/40
LV25450PNW no.a1668-2/40 specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit v cc 8v osc_v cc (3), ifagc_v cc (27), ifagcout-drive_v cc (35), fe_v cc (61) 9.0 v maximum supply voltage v cc 5v xtal_v cc (16), digital_v cc (25), analog_v cc (41) 6.0 v ccb bus maximum input voltage v in max pin 21, 22, 23 -0.3 to +5.0 v ccb bus maximum output voltage v o pin 24 -0.3 to +6.5 v allowable power dissipation pd max ta 85 c * 850 mw operating temperature topr -40 to +85 c storage temperature tstg -50 to +150 c * : using the circuit board for the sanyo tuner module (specified board : 55mm 39mm 1.3mm, glass epoxy) recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit v cc 8v osc_v cc (3), ifagc_v cc (27), ifagcout-drive_v cc (35), fe_v cc (61) 8.0 v recommended supply voltage v cc 5v xtal_v cc (16), digital_v cc (25), analog_v cc (41) 5 v v cc 8vop 7.5 to 8.5 v operating supply voltage range v cc 5vop 4.5 to 5.5 v ccb bus high-level input voltage v ih ce, di, cl 2.5 to 5.0 v ccb bus low-level input voltage v il ce, di, cl 0 to 0.8 v ccb bus high-level input current i ih ce, di, cl ; vi5.5v 10 or less a ccb bus low-level input current i il ce, di, cl ; vi0v 10 or less a do low-level output voltage v ol 0.38 or less v do high-level output voltage v oh connected to an lc75045. 2.1 or more v reception frequencies parameter symbol conditions frequency ratings unit fm reception frequencies f fm jpn, us, eu, e-eu 65 to 108.1 mhz fm weather band reception frequencies f fm-wb 162.4 to 162.55 mhz f amlw lw 144 to 288 khz fammw mw 520 to 1710 khz am reception frequencies famsw sw 2.94 to 22.0 mhz
LV25450PNW power on/power off timing and the power on reset recommended operating ratings at ta = 25c, gnd = 0v ratings parameter symbol conditions min typ max unit vcop h pin 3, 27, 35, 54, 55, 61 7.5 8.5 v operating supply voltage vcop l pin 16, 25, 41 4.5 5.5 v vreg3 pin 26 2.7 3.3 v internal logic voltage vreg4 pin 15 3.7 4.3 v power application time (8.0 v 5.0 v) t7 10 100 ms vhmin3 pin 26 : design reference value vreg3 2.2 v internal register retention voltage vhmin4 pin 15 : design reference value vreg4 2.2 v internal register reset voltage voff pin 16, 25, 41 : design reference value 0 0.2 v internal register reset power supply rise time tpor pin 16, 25, 41 : design reference value 0.05 3 ms power application time (5.0 v 8.0 v) t14 10 100 ms power-on sequence and power-on reset (1) power on image and power on reset recommended operating ratings at ta = 25c, gnd = 0v ratings parameter symbol conditions min typ max unit vcop h pins 3, 27, 35, and 61 7.5 8.5 v operating supply voltage vcop l pins16, 25, and 41 4.5 5.5 v vreg3 pin 26 2.7 3.3 v internal logic voltage vreg4 pin 15 3.7 4.3 v vhmin3 pin 26 : design reference value 2.2 vreg3 v internal register retention voltage vhmin4 pin 15 : design reference value 2.2 vreg4 v internal register reset voltage voff pins 16, 25, and 41 : design reference value 0 0.2 v internal register reset power supply rise time tpor pins 16, 25, and 41 : design reference value 0.05 3 ms note 1 : when reading out data from pin d0 connection (e.g., e2prom ) with the voltage at the pin 23 below 2.2v, be sure to read the data after transmitting the control data and pin d0 being set ?open? because the state of internal register cannot be specified. note 2 : it is necessary to set data when power is first applied or there is a momentary power interruption. v cc _8vop v cc _5vop vreg4 vreg3 vhmin3 vhmin4 voff tpor image of supply voltage no.a1668-3/40
LV25450PNW (2) power on/off sequence the power on and power off sequences for th e ic must follow the order shown below. ? power on sequence no.a1668-4/40 ? power off sequence tpup85 8v system power 5v system power period when power is applied to each pin 8v system power 5v system power tpdn58 ratings parameter symbol conditions min typ max unit power on period (8v 5v) tpup85 0 100 ms power off period (5v 8v) tpdn58 0 100 ms never apply power to the ic until all the supply voltages reach the predetermined values. for pin d0, refer to the above section (1), note 1, and note 2. regarding voltage applied to each power pin, 8v system must always be higher than 5v system (8v system > 5v). as long as this relationship is maintained and the power supply rise/fall time is within 100ms, there is no problem if the low voltage side power is started up first.
LV25450PNW no.a1668-5/40 ac characteristics operating characteristics at ta = 25c, v cc = 8.0v, v dd = 5.0v, unless otherwise spec ified. ratings for publications * : these measurements are made using the yamaichi electro nics ic51-0644-807 ic socket. an ihf bandpass filter is used as the audio filter. fm characteristics - fm front end mixer input (no dummy) applied voltage ccb command parameter symbol conditions pin 28 pin 34 pin 50 pin 2 in1 in2 in3-1 in3-2 min typ max unit dc characteristics current drain-8v fm i cco -8v fm no input, fm mode i3+i27+i355+i54+i55+i61 3 15 13 25 25 43.2 54 64.8 ma current drain-5v fm i cco -5v fm no input, fm mode i16+i25+i41 3 15 13 25 25 20.8 26 31.2 ma regulator bias 3v vreg3v the pin 26 voltage 3 15 13 25 25 2.7 3 3.3 v regulator bias 4v vreg4v the pin 15 voltage 3 15 13 25 25 3.6 4 4.4 v fm antenna dump output current iantd-f the pin 64 output current (pin 64 load = 100 +pin_diode 2 when 6.0v is applied to pin 2 0 0 6 15 13 25 25 4.5 7.5 11 ma ac characteristics crystal oscillator frequency fxtal d2-7, 6, 5 = [100] 3 15 13 25 25 4.5 mhz crystal oscillator level vxtal d2-7, 6, 5 = [100] (reference value) d32-08 = 0, d2-10, 9, 8 = [100] 3 15 13 25 25 15 mvrms crystal oscillator buffer level vxtal osc out2 d2-7, 6, 5 = [100] (reference value) d32-08 = 0, d2-10, 9, 8 = [100] 3 15 13 25 25 115 165 mvrms vsmfm-1 10db v, the pin 34 dc output, no modulation 3 15 13 25 25b 0.65 0.95 1.25 v vsmfm-2 30db v, the pin 34 dc output, no modulation 3 15 13 25 25b 0.95 1.25 1.55 v vsmfm-3 50db v, the pin 34 dc output, no modulation 3 15 13 25 25b 2.10 2.15 2.20 v vsmfm-4 70db v, the pin 34 dc output, no modulation 3 15 13 25 25b 3.1 3.4 3.7 v s-meter dc output * : adjust the shifter-bits with a 50db v input so that vsm is set to 2.15v. vsmfm-5 90db v, the pin 34 dc output, no modulation 3 15 13 25 25b 3.7 4 4.3 v total gain from mixer to div if amplifier gmxdiv fm_mix_in, div_out_if (pin 32) ratio of the input to output signal levels 98.1mhz mod = off, 70db v-input 1.5 15 13 25 25 16 19 22 db div if amplifier gain gdivif if_n_in1 (pin 46), div_out_if (pin 32) ratio of the input to output signal levels 10.7mhz mod = off, 88db v-input 3 15 13 25 25 4.5 7.5 10.5 db 1db compression point driver if 1db point dif if_n_in1 (pin 46), div_out_if (pin 32) ratio of the input to output signal levels 10.7mhz mod = off 3 15 13 25 25 111 db narrow if agc grain (fm) gifagcnf1 fm_analog_in (pin 46), 10.7outn (pin 30) ratio of the input to output signal levels 10.7mhz mod = off 100db v-input d32-27 to 25 = 011 0 15 13 25 25 -4.5 -2.5 -0.5 db narrow if agc grain (fm) gifagcnf2 fm_analog_in (pin 46), 10.7outn (pin 30) ratio of the input to output signal levels 10.7mhz mod = off 80db v-input d32-27 to 25 = 011 3 15 13 25 25 23.5 25.5 27.5 db 1db complession point fm-narrow 1db point nf fm_analog_in (pin 46), 10.7outn (pin 30) 10.7mhz mod = off d32-27 to 2] = 011 0 15 13 25 25 107 db v continued on next page.
LV25450PNW no.a1668-6/40 continued from preceding page. applied voltage ccb command parameter symbol conditions pin 28 pin 34 pin 50 pin 2 in1 in2 in3-1 in3-2 min typ max unit image cancellation ratio (us) ir us 98.1mhz reference, the amount rejected at +21.4mhz trm-bit d2-18=[0]:on apf-adj d32-19 to 16=[1010]:10 1.5 15 21 25 58 30 db image cancellation ratio (jpn) ir jpn 83mhz reference, the amount rejected at -21.4mhz d1-28 to 26 = [010] trm-bit d2-18=[1]:off apf-adj d32-19 to 16=[1000]:8 1.5 22 13 27 25 25 db fm wide agc on sensitivity f1 wagc on-f1 fr = 102.1mhz fm-wide agc-bit d32-3 to 0 = [0000] : minimum 0 3 15 13 25 13 78 85 92 db v fm wide agc on sensitivity f2 wagc on-f2 fr = 102.1mhz fm-wide agc-bit d32-3 to 0 = [1111] : maximum 0 3 15 13 25 15 92 99 106 db v fm narrow agc on sensitivity f1 nagc on-f1 fr = 98.1mhz fm-narrow agc-bit d32-7 to 4 = [0000] : minimum 0 3 15 13 25 16 70 77 84 db v fm narrow agc on sensitivity f2 nagc on-f2 fr = 98.1mhz fm-narrow agc-bit d32-7 to 4 = [1111] : maximum 0 3 15 13 25 18 86 93 100 db v practical sensitivity s/n-31 connected to an la1787 (mpx, left channel output) *hcc off 98.1mhz, 31db v, fm = 1khz, 22.5khz-mod 62/63pin input 3 15 13 25 25 30 db signal-to-noise ratio s/n-90 connected to an la1787 (mpx, left channel output) 98.1mhz, 90db v, fm = 1khz, 22.5khz-mod 62/63pin input 0 15 13 25 25 54 57 db am characteristics : am, am-ant inputs applied voltage ccb command parameter symbol conditions pin 28 pin 34 pin 50 pin 2 in1 in2 in3-1 in3-2 min typ max unit dc characteristics current drain-8v am i cco -8v am no input, am mode i3+i27+i35+i54+i55+i61 3 33 15 26 26 36 46 56 ma current drain-5v am i cco -5v am no input, am mode i16+i25+i41 3 33 15 26 26 15 19 23 ma am antenna dump output current iantd-a when pin 50 is connected to ground the ant-d (pin 52) output current 3 0 33 15 26 26 3.5 6 9 ma ac characteristics first am amplifier gain gamp1 fm_n_in1 (pin 46) if_out (pin 44), after cf matching, 10.7mhz mod = off 74db v = input 0 33 15 26 26 5.2 6.2 7.2 db narrow if agc grain (am) gifagcna1 am_analog_in (pin 39), 10.7outn (pin 30) ratio of the input to output signal levels 10.7mhz mod = off 100db v-input d32-27 to 25 = [011] 0 33 15 26 26 -4.5 -2.5 -0.5 db narrow if agc grain (am) gifagcna2 am_analog_in (pin 39), 10.7outn (pin 30) ratio of the input to output signal levels 10.7mhz mod = off 80db v-input d32-27 to 25 = [011] 3 33 15 26 26 23.5 25.5 27.5 db 1db compression point am - narrow 1db point na am_analog_in (pin 39), 10.7outn (pin 30) 10.7mhz mod = off d32-27 to 25 = [011] 0 33 15 26 26 107 db v continued on next page.
LV25450PNW continued from preceding page. applied voltage ccb command parameter symbol conditions pin 28 pin 34 pin 50 pin 2 in1 in2 in3-1 in3-2 min typ max unit am wide-agc on sensitivity a1 wagc on-a1 am-ant-in = 1.4mhz, mod = off the input level such that the ant_d (pin 52) level becomes 0.5v. am wide agc-bit d32-3 to 0 = [0000] 0 33 15 26 27 78.5 83.5 88.5 db v am wide agc on sensitivity a2 wagc on-a2 am-ant-in = 1.4mhz, mod = off the input level such that the ant_d (pin 52) level becomes 0.5v. am wide agc-bit d32-3 to 0 = [1101] 0 33 15 26 29 92 97 102 db v am narrow agc on sensitivity a1 nagc on-a1 am-ant-in = 1mhz, mod = off the input level such that the ant_d (pin 52) level becomes 0.5v. am narrow agc-bit d32-7 to 4 = [0000] 0 33 15 26 30 60 65 70 db v am narrow agc on sensitivity a2 nagc on-a2 am-ant-in = 1mhz, mod = off the input level such that the ant_d (pin 52) level becomes 0.5v. am narrow agc-bit d32-7 to 4 = [1111] 0 33 15 26 32 75 80 85 db v total am gain amgain 1mhz, 60db v, mod = off, the ration of the am_ant input and the 10.7outn (pin 30) output levels 3 33 15 26 26 36 41 46 db practical sensitivity s/n-33 with an la1787 connected with a 1mhz, 33db v, fm = 1khz, 30% modulation ant input and the if agc voltage = 3v add. 3 33 15 26 26 20 db am-thd thd-74 with an la1787 connected with a 1mhz, 74db v, fm = 1khz, 80% modulation ant input and the if agc voltage adjusted so that the ifagcout level is 100db v. adjusted 33 15 26 26 0.7 1.0 % signal-to-noise ratio s/n-74 with an la1787 connected with a 1mhz, 74db v, fm = 1khz, 30% modulation ant input and the if agc voltage adjusted so that the ifagcout level is 100db v. adjusted 33 15 26 26 52.5 56 db package dimensions unit : mm (typ) 3190a 10.0 10.0 12.0 12.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (1.25) 11 6 17 32 33 48 49 64 sanyo : sqfp64(10x10) no.a1668-7/40
LV25450PNW no.a1668-8/40 test data pattern pll in1 data ccb address control data 1 control data 2 control data 3 control data 4 in1 data contents a0 a1 a2 a3 a4 a5 a6 a7 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 osc_d1 osc_d2 am/fm dvs r0 r1 r2 r3 osc_div wb delay_adj0 delay_adj1 delay_adj2 - - - - fmfil amfil pll counter value delay-adj 15 fm_us98.1m fref = 100khz 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 2176 0 22 fm_jp83m fref = 100khz, delay = 1 0 0 0 1 0 1 0 0 1 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 2169 1 33 mw1000k fref = 10k (usa) 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 23400 0 pll in2 data ccb address control data 1 control data 2 control data 3 control data 4 in2 data contents a0 a1 a2 a3 a4 a5 a6 a7 - - - - - - - - - - - - - - - - - - - - x_sw_0 x_sw_1 x_sw_2 xlvl0 xlvl1 xlvl2 alc_off - - - - - - - - - - - - - - - - - - - - - - - - offset_sw - - - - uld ul0 ul1 two_doff - - - - - - - - dz0 dz1 dlc test0 test1 test2 x'tal-adj x'tal-level 13 fm reception mode settings (trm=off) 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 0 0 4 4 15 mw reception mode settings 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 4 4 21 fm reception mode settings (trm=on) 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 4 4 pll in3-1 data ccb address control data 1 control data 2 control data 3 control data 4 in3-1 data contents a0 a1 a2 a3 a4 a5 a6 a7 rfdac0 rfdac1 rfdac2 rfdac3 rfdac4 rfdac5 rfdac6 rfdac7 rfdac8 tuneroff antdac0 antdac1 antdac2 antdac3 antdac4 antdac5 antdac6 antdac7 antdac8 reg_adj0 reg_adj1 xs0 xs1 dac9_sw2 dac9_sw iqmix_gain iq_sw fmagc_on amagc_on ifagc_off dtestsw sub-address rf-dac ant-dac 1 bit-check-0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2 bit-check-1 1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 3 bit-check-2 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 2 5 bit-check-4 1 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 4 4 6 bit-check-7 1 0 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 7 7 7 bit-check-8 1 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 8 8 8 bit-check-15 1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 15 15 9 bit-check-16 1 0 0 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 16 16 10 bit-check-31 1 0 0 1 0 1 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 31 31 11 bit-check-32 1 0 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 32 32 12 bit-check-63 1 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 63 63 13 bit-check-64 1 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 64 64 14 bit-check-127 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 127 127 15 bit-check-128 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 128 128 16 bit-check-255 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 255 255 17 bit-check-256 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 256 256 18 bit-check-511 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 511 511 25 standard fm (upper) 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 256 256 26 standard fm 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 standard fm (lower) 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 256 256 30 tuner-off(fm) 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 256 256 pll in3-2 data ccb address control data 1 control data 2 control data 3 control data 4 in3-2 data contents a0 a1 a2 a3 a4 a5 a6 a7 w_agc0 w_agc1 w_agc2 w_agc3 n_agc0 n_agc1 n_agc2 n_agc3 eva2 (xtal) - - - - - - - - vreg4v_off key_agc0/rfagc_h0 key_agc1/rfagc_h1 key_agc2/rfagc_h2 key_agc3/rfagc_h3 apf_adj0/rfagc_s0 apf_adj1/rfagc_s1 apf_adj2/rfagc_s2 apf_adj3/rfagc_s3 s_meter0 s_meter1 s_meter2 s_meter3 s_meter4 adj_n0 adj_n1 adj_n2 - - - - fmfetoff w_keyed sub-address wide-agc narrow-agc keyed-agc am-rfagc hard am-rfagc soft fm-s-meter shifter ifagc-amp gain 13 fm (w-agc-bit = 0) 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1 0 7 0 7 7 15 3 15 fm (w-agc-bit = 15) 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1 15 7 0 7 7 15 3 16 fm (n-agc-bit = 0) 1 0 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1 7 0 0 7 7 15 3 18 fm (n-agc-bit = 15) 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1 7 15 0 7 7 15 3 25 standard fm-2 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1 7 7 0 7 7 15 3 25b standard fm-2 vsm-shifter after the adjusting 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 * * * * * 1 1 0 0 0 0 1 7 7 0 7 7 adjust- ment 3 26 standard am-2 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 7 7 0 6 12 15 3 27 am (w-agc-bit = 0) 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 0 7 0 6 12 15 3 29 am (w-agc-bit = 13) 1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 13 7 0 6 12 15 3 30 am (n-agc-bit = 0) 1 0 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 7 0 0 6 12 15 3 32 am (a-agc-bit = 15) 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 7 15 0 6 12 15 3 58 standard fm-2 trm=on apf-adj=10 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 1 1 1 0 1 1 0 0 0 0 1 7 7 1 7 5 15 3 items marked with an asterisk are vs m adjustment items. the bit values after adjustment must be retained.
LV25450PNW power dissipation test board material : glass epoxy resin conditions : double-sided circuit board, without chassis board size : 55mm 39mm 1.3mm no.a1668-9/40 * ratings for LV25450PNW power dissipation is measured using the above circuit board.
LV25450PNW no.a1668-10/40 pin functions pin no. pin name pin no. pin name 1 fe_gnd 33 ifagcout-drive gnd 2 fm-rf-agc 34 vsm_dc 3 local-osc-v cc 8v 35 ifagcout-drive v cc 4 local-osc (b) 36 vreg2.7v 5 local-osc (c) 37 analog_gnd 6 local-osc_gnd 38 am analog in bypass 7 vt (lpf) 39 am analog in 8 fet_gnd 40 (non-connection) 9 pll-lpf_am 41 analog_v cc 5v 10 fm_fet_out 42 am _n-agc pick-up 11 am_fet_out 43 address-sw 12 am_cp out 44 am 1stif_amp_out 13 fm_cp out 45 vreg4.9v 14 digital_gnd 46 if-i n-n1 (cf = 180k) 15 vreg 4v 47 if-in-n_bypass 16 xtal-v cc 5v 48 (non-connection) 17 xtal-in 49 am-w-agc 18 xtal-out 50 am-rf-agc 19 xtal-gnd 51 am rf-agc (bypass) 20 xtal_osc_out2 52 am-ant-d 21 ce 53 fm n-agc-in 22 di 54 mix-out 23 cl 55 mix-out 24 do 56 ant-dac 25 digital_v cc 5v 57 rf-dac 26 vreg 3v 58 (non-connection) 27 ifagcamp_v cc 8v 59 am-mix-in2 (bypass) 28 agc_dac_s (fromdsp) 60 am-mix-in1 29 ifagcamp_gnd 61 fe v cc _8v 30 ifagc-out (10.7mhz) n 62 fm-mix-in1 31 ifagc-out (10.7mhz) p 63 fm-mix-in2 32 div_if-out 64 fm-ant-d
LV25450PNW no.a1668-11/40 functions am/fm front-end agc block fm image rejection mixer (iq-mix) gain switching : 1 bit fm iq-mix phase adjust (f or the japanese fm band) injection switching 1 bit for east band receive am double balance mixer pin diode drive agc output (am/fm) wide agc sensitivity setting (am/fm) 4 bit dac narrow agc sensitivity setting (am/fm) 4 bit dac keyed agc adjust (fm) 4 bit dac am rf agc 4 bit dac local oscillator 133mhz to 262mhz local osc divider (fm/am) division by 1, 2, or 3 local osc divider (am) division by 20, 16, 12, or 8 ant/rf dac (fm) 9 bit dac 2 am 1st if amp block 1st-if amplifier 10.7m if-lim-amp/s-meter block s-meter shifter 5 bit dac if limiter amplifier 6 stage for fm-s-meter s-meter (dc for keyed agc) (fm) if-agc-amp/if-amp for diversity block if agc amplifier (control voltage from dsp) if output driver for dsp 10.7mhz if ifagc-amp gain adjust. if-amplifier for diversity (fixed gain) 10.7mhz if if-output driver for div-if 10.7mhz if pll fast lock pll filter sw charge-pomp switching other tuner off 1 bit sw 2.7v regurator adjust 2 bit dac
LV25450PNW LV25450PNW level diagrams fm level diagram 0 20 40 60 80 100 120 ant in db v ant antd fet amp iq mixer cf (180k) ifagc amp block level [dbv] antin = 45.6dbv antin = 5dbv antin = 65dbv antin = 120dbv am level diagram 0 20 40 60 80 100 120 ant in ant dummy antd rf amp mixer cf (180k) 1st-if amp xtal filter (6k) ifagc amp block signal level [db v] antin = 45.6dbv antin = 5dbv antin = 65dbv antin = 120dbv near practical sensitivity ifagc-on rfagc-on strong input signal 24 56.3 80 120 full gain ant in 7.5 39.8 63.5 103.5 -16.5 ant dummy 7.5 39.8 63.5 63.5 0 antd 29 61.3 85 85 21.5 rf amp 39.5 71.8 95.5 95.5 10.5 mixer 36 68.3 92 92 -3.5 cf (180k) 41.2 73.5 97.2 97.2 -1 xtal filter (6k) 42.2 74.5 98.2 98.2 6.2 1st-if amp 66.7 99 99 99 25.5 ifagc amp near practical sensitivity ifagc-on rfagc-on strong input signal fet : fet application fm (fet) gain down a m 5.0 43.6 65.0 120.0 ant in dbv 1.5 40.1 61.5 116.5 -3.5 ant 1.5 40.1 61.5 68.1 0 antd 24.4 63.0 84.4 91.0 22.9 fet amp 37.9 76.5 97.9 104.5 13.5 iq mixer 34.9 73.5 94.9 101.5 -3 cf (180k) 55.4 total gain 60.4 99.0 99.0 99.0 25.5 ifagc amp no.a1668-12/40
LV25450PNW block diagram 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 8v 5v 5v 8v 8v 5v 8v l p f l p f xtal 4.5mhz mix coil am mixer/ fm iq-mixer ecl2 1/4,1/6 1/8,1/10 wide agc am 1st amp limitter amp singal meter keyed agc narrow agc rf agc ant-d ant dac rf dac ecl1 1/1,1/2 1/3 vco if gain variation correction (narrow output) 9bit-dac temperature characteristics compensatioin slope switching am rf- agc compalate s-meter shifter iq-mixer gain-adj tuner adjustment fm agc am rf- agc amp sens fm apf adj fm keyed-agc am/fm n-agc am/fm w-agc in 3-1 in 3-2 in 1 in 2 wide agc narrow agc rf agc ant-d am agc pll swallow counter p-ctr phase det charge pump r-ctr power on reset nmos tr computer control bus xtal osc 3v reg 4v reg 4.9v reg s-meter (main/sub) 2.7v reg am amp fm amp if- driver analog if agc amp diver if buffer if agc amp xtal-osc freq. adj xtal-osc level adj xtal filter_16khz cf10.7mhz_180k coil tuning circuit am rf amplifier circuit bpf am antenna circuit fm rf amplifier circuit fm rf tuning circuit no.a1668-13/40
LV25450PNW pin description pin no. pin function description equivalent circuit 1 fe.gnd front-end block gnd 2 fm-rf-agc fm rf agc voltage output 30k 500 500 500 500 v cc 12k 2 3 local-osc-v cc 8v local oscillator system power supply 4 5 local-osc (b) local-osc (c) oscillator pins v cc _3pin 4.5v 5 4 dc-offset circuit 6 local-osc-gnd local oscillator system gnd 7 vt (lpf) 12 12 100 7 8 fet_gnd active filter fet gnd in the pll circuit block 9 pll-lpf_am 12 12 5.5k 9 10 fm_fet_out 12 12 100 10 continued on next page. no.a1668-14/40
LV25450PNW continued from preceding page. pin no. pin function description equivalent circuit 11 am_fet_out 12 12 100 11 12 am_cp out 12 12 200 12 13 fm_cp out 12 12 200 13 14 digital_gnd digital system gnd 15 vreg 4v dedicated swallow counter 4v regulator voltage smoothing 5k 15 v cc v cc (25pin) v dd pll 35k dac 16 xtal-v cc 5v dedicated crystal oscillator power supply 17 18 xtal-in xtal-out connect a 4.5mhz crystal resonator between pins 17 and 18. connect a 10pf capacitor between pin 17 and gnd, and a 150pf capacitor between pin 18 and gnd. v cc (pin16) es6 500 500 333 333 333 1k 20k 1k 1.5k 5k 5k 500 35pf 8pf 4pf 2pf 1.5k 1.5k 1.5k 1.5k 1.5k 20 17 18 amp amp amp alc to pll 19 xtal-gnd dedicated crystal oscillator gnd continued on next page. no.a1668-15/40
LV25450PNW continued from preceding page. pin no. pin function description equivalent circuit 20 xtal_osc_out2 pin 20: clock signal output for 2-tuner 21 ce serial data input (de) to the LV25450PNW. force the output to the high level during serial data output (do). 3v v ss (pin14) 1k p-mos p-mos n-mos n-mos 21 22 di input for the serial data transferred to the LV25450PNW from the controller. 3v v ss (pin14) 1k p-mos p-mos n-mos n-mos 22 23 cl clock used for synchronization when serial data is input to the LV25450PNW (di) or when serial data is output (do). 3v v ss (pin14) 1k p-mos p-mos n-mos n-mos 23 continued on next page. no.a1668-16/40
LV25450PNW continued from preceding page. pin no. pin function description equivalent circuit 24 do output for data transferred to the controller by the LV25450PNW v ss (pin14) v ss (pin12) 500 500 24 25 digital_v cc 5v digital system power supply 26 vreg3v 3v regulator output for pll power supply 5k 26 v cc v cc (25pin) v dd pll 41.7k dac 27 ifagcamp_v cc 8v if (10.7mhz) signal system power supply 28 agc_dac_s if agc control bias is supplied from the lc7504x (for the analog system). 28 8k 4.1k 1k 1k 8k 4.1k 29 ifagcamp_gnd if (10.7mhz) signal system gnd continued on next page. no.a1668-17/40
LV25450PNW continued from preceding page. pin no. pin function description equivalent circuit 30 ifagc-out (10.7mhz) n narrowband if (10.7mhz) signal differetial output to the lc7504x for analog use. 50 250 250 50 v cc (33pin) 30 31 ifagc-out (10.7mhz) p narrowband if (10.7mhz) signal differential output to the lc7504x for analog use. 50 250 250 50 v cc (33pin) 31 32 div_if-out driver 10.7mhz signal buffer output 10k 200 200 v cc (61pin) 32 14.5 33 ifagcout-drive gnd dedicated ifagc output driver gnd 34 vsm_dc current driver s-meter output ac components are removed with an external capacitor. v cc (41pin) v cc (61pin) 300 1k 10k 34 continued on next page. no.a1668-18/40
LV25450PNW continued from preceding page. pin no. pin function description equivalent circuit 35 ifagcout-drive v cc dedicated ifagc output driver v cc 36 vreg2.7v 2.7v internal regulator output (smoothing) 333 36 1k 30k v cc (pin61) 37 analog_gnd analog system gnd 38 39 am analog in bypass am analog in pin 39 : am analog signal input to the am ifagc amplifier. (am 10.7mhz if signal) pin 38 : connected to ground with an external bypass capacitor. 335 38 10k 9k 3.4v 9k 335 39 2.3k 40 n.c. 41 analog_v cc 5v analog system power supply 42 am narrow-agc pick-up am narrow agc detection input 42 10k 500 500 43 address_sw when two tuners are used, one (for substitute) of the two ics?pin 43 is connected to ground, need changes the sddress. 43 1k continued on next page. no.a1668-19/40
LV25450PNW continued from preceding page. pin no. pin function description equivalent circuit 44 am 1stif_amp_out first am if amplifier output 44 333k 50 v cc (pin61) 45 vreg4.9v 4.9v internal regulator output (smoothing) 1k 34 15k 50k 45 335 46 47 if-in-n1 if-in-n_bypass first am if amplifier input driver 10.7mhz signal buffer input fm limiter amplifier input 47 550 500 500 335 335 300 300 v 270 500 500 20pf 20pf 500 500 46 48 n.c. 49 am-w-agc am wide agc pickup 49 1k 1k 10k continued on next page. no.a1668-20/40
LV25450PNW continued from preceding page. pin no. pin function description equivalent circuit 50 am-rf-agc rf agc rectifying capacitor determines the distortion for low-frequency modulation. increasing the size of c50 : distortion improves response becomes slower reducing the size of c50 and c 51 : distortion degrades response becomes faster v cc (61pin) 100 500 15k 750 50 1k 51 am-rf-agc (bypass) reducing the size of c51 : distortion degrades response becomes faster 51 50k 500 1k 52 am-ant-d provides the pin diode drive current. this is the antenna dumping current output. 200 500 v cc_8v 52 53 fm n-agc-in fm narrow agc input 53 2.5k 2.2v 1k 10k 54 55 mix-out mix-out mixer output (common to fm and am) 55 54 fm mix am mix continued on next page. no.a1668-21/40
LV25450PNW continued from preceding page. pin no. pin function description equivalent circuit 56 ant-dac antenna tuning circuit adjustment d/a converter output (9-bit d/a converter) 1k 1k 1k 1k 1k 56 57 rf-dac rf tuning circuit adjustment d/a converter output (9-bit d/a converter) 1k 1k 1k 1k 1k 57 58 n.c. 59 60 am mix-in2 (bypass) am mix-in1 am mixer input input impedance : 10k 110 110 2.5k 10k 10k 12k v cc (pin61) 60 59 61 fe v cc 8v front-end block power supply 62 63 fm mix-in1 fm mix-in2 fm mixer input fm wide agc pickup input impedance : 10k 63 500 fm mix agc amp 10k 10k 3.6v 500 62 continued on next page. no.a1668-22/40
LV25450PNW continued from preceding page. pin no. pin function description equivalent circuit 64 fm ant d pin 64 : the antenna driving current flows when the rf agc voltage reaches (v cc - vbe). 64 v cc 300 300 75k no.a1668-23/40
LV25450PNW serial bus data timing ce : chip enable cl : clock di : data input do : data output (pin information only) tch teh tes thd tsu old new tlc tel tcl v il v ih v ih v ih v ih v ih v ih v ih v il v il v il internal data latch cl di ce ?? when cl is stopped at the l level ?? tcl teh tes thd tsu old new tlc tel tch v il v ih v ih v ih v ih v ih v ih v il v il v il internal data latch cl di ce ?? when cl is stopped at the h level ?? parameter symbol pin conditions min typ max unit data setup time tsu di, cl 0.45 s data hold time thd di, cl 0.45 s clock l-level time tcl cl 0.45 s clock h-level time tch cl 0.45 s ce wait time tel ce, cl 0.45 s ce setup time tes ce, cl 0.45 s ce hold time teh ce, cl 0.45 s data latch change time tlc 0.45 s data input high-level voltage v ih cl, di, ce 2.5 5.0 v data input low-level voltage v il cl, di, ce 0 0.8 v no.a1668-24/40
LV25450PNW serial data i/o procedures the LV25450PNW uses the sanyo audio ic serial bus format. data is input and output using a ccb (computer control bus). the LV25450PNW adopts an 8-bit address version of the ccb format. address i/o mode b0 b1 b2 b3 a0 a1 a2 a3 contents in1 0 0 0 1 0 1 0 0 [1] in1b 0 1 0 1 0 1 0 0 ? control data input mode. pll setup ? 32 bits of data are input ? in1b is the 2-tuner mode address (when pin 43 is tied to ground) in2 1 0 0 1 0 1 0 0 [2] in2b 1 1 0 1 0 1 0 0 ? control data input mode. pll setup ? 32 bits of data are input ? in2b is the 2-tuner mode address (when pin 43 is tied to ground) in3 1 0 0 1 0 1 1 0 [3] in3b 0 0 0 1 0 1 1 0 ? the tuner block is set up in control data input (serial data input) mode. ? 32 bits of data are input - there is a sub-address ? in3b is the 2-tuner mode address (when pin 43 is tied to ground) first data in1/2 a3a2a1a0b3 b2 b1 b0 di i/o mode determined ce cl i) serial data inputs (in1/in2/i n3) tsu, thd, tes, tel, teh > 0.45 s tlc < 0.45 s ce cl tsu thd dt b0 b1 b2 b3 a0 a1 a2 a3 p0 p1 p2 p3 * cts gt0 gt1 internal data tel tes tlc teh (*1) since the do pin is an n-channel open drain circuit, the times for the data to change will differ depending on the value of the pull-up resistor and printed circuit board capacitance. (*2) the do pin is normally left open. no.a1668-25/40
LV25450PNW d1-00 d1-01 d1-02 d1-03 d1-04 d1-05 d1-06 d1-07 d1-08 d1-09 d1-10 d1-11 d1-12 d1-13 d1-14 d1-15 d1-16 d1-17 d1-18 d1-19 d1-20 d1-21 d1-22 d1-23 d1-24 d1-25 d1-26 d1-27 d1-28 d1-29 d1-30 d1-31 p00 p01 p02 p03 p04 p05 p06 p07 p08 p09 p10 p11 p12 p13 p14 p15 osc d1 osc d2 am/fm dvs r0 r1 r2 r3 osc_div wb delay_adj0 delay_adj1 delay_adj2 0 fmfil amfil llll (8) (7) (6) (5) (4) (3) (2) (1) lllllll l l - - - - - - - - - - - - - - - - hh h dvs 0 1 program-ctr stop program-ctr normal operation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0000 0000 0000 0101 1010 1111 divide by 272 divide by 500 divide by 1000 divide by 2000 divide by 21845 divide by 43690 divide by 65535 : : : : : : : : : : : : 000 010 100 000 010 101 111 0001 0001 0011 0111 0101 1010 1111 0001 1111 1110 1101 0101 1010 1111 100khz 50khz 25khz 25khz 12.5khz 6.25khz 3.125khz 3.125khz 10khz 9khz 5khz 1khz 3khz 30khz illegal value illegal value am/fm 0 1 0 1 0 1 osd d2 0 0 1 1 osd d1 divisor by 10 divisor by 8 divisor by 6 divisor by 4 divisor fm am a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 0 0 1 0 1 0 0 0 in1 setting am oscillator divisor control 0 0 1 1 wb 0 1 0 1 osd div divide by 2 divide by 3 divide by 1 divide by 1 divisor am/fm/wb oscillator divide control pll filter switching programmable counter divisor setting (from 272 to 65535) fm-iqmix phase_adjust *wb : select 1 for weather band reception 0 0 0 0 1 1 1 1 delay_adj2 0 0 1 1 0 0 1 1 delay_adj1 0 1 0 1 0 1 0 1 delay_adj0 small large adjustment amount in address code reference frequency setting normal filter state am/fm amfil fmfil 0 1 off on on off lsb msb no.a1668-26/40
LV25450PNW d2-00 d2-01 d2-02 d2-03 d2-04 d2-05 d2-06 d2-07 d2-08 d2-09 d2-10 d2-11 d2-12 d2-13 d2-14 d2-15 d2-16 d2-17 d2-18 d2-19 d2-20 d2-21 d2-22 d2-23 d2-24 d2-25 d2-26 d2-27 d2-28 d2-29 d2-30 d2-31 0 0 0 0 0 x_sw_0 x_sw_1 x_sw_2 xlvl0 xlvl1 xlvl2 alc_off 0 0 0 0 0 0 offset_sw 0 uld ul0 ul1 two_doff 0 0 dz0 dz1 dlc test0 test1 test2 llll (17) (16) (18) (14) (15) (13) (9) (10) (11) (12) lllllll l lllllllhlllllhlll ll l charge pump control 0 1 normal operation stopped buffer output x?tal-osc 0 1 normal operation stopped switch alc_on/off 0 1 alc_off normal operation (alc_on) a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 0 0 1 0 1 0 0 1 in2 setting x?tal osc frequency fine adjustment in address code lsb msb 000 001 010 011 100 101 110 111 x?tal osc oscillation level fine adjustment 000 001 010 011 100 101 110 111 do pin control data uld do pin low when not locked. open 0 1 ic test mode these bits are normally set to : test0 = 0 test1 = 0 test2 = 0 unlock detection switching 0 0 1 1 dz1 0 1 0 1 dz0 dza dzb dzc dzd dead zone mode dead zone control 0 0 1 1 ul1 ul0 0 1 0 1 detection pin output ic internal signals i/o ports control data 0 : input, 1 : output normally set to 0. (37) (37) lo-osc dc offset giving function d2-18 offset giving switch sw offset giving on offset giving off 0 1 no.a1668-27/40
LV25450PNW tuner off setting 0 1 normal operation tuner off iq mixer gain adjustment 0 1 gain down gain up ifagc-amp 0 1 on off iqmix phase switching 0 1 lower upper fm agc on 0 1 normal on am agc on 0 1 normal on 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001000 111111010 111111011 111111100 111111101 111111110 111111111 0.4v 7.1v a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 0 1 1 0 1 0 0 1 0 in3-1 tuner setting 1 address 69h, subaddress[0] in address code sub address code ant-dac 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001000 111111010 111111011 111111100 111111101 111111110 111111111 0.4v 7.1v rf-dac d31-00 d31-01 d31-02 d31-03 d31-04 d31-05 d31-06 d31-07 d31-08 d31-09 d31-10 d31-11 d31-12 d31-13 d31-14 d31-15 d31-16 d31-17 d31-18 d31-19 d31-20 d31-21 d31-22 d31-23 d31-24 d31-25 d31-26 d31-27 d31-28 d31-29 d31-30 d31-31 rfdac0 rfdac1 rfdac2 rfdac3 rfdac4 rfdac5 rfdac6 rfdac7 rfdac8 tuneroff antdac0 antdac1 antdac2 antdac3 antdac4 antdac5 antdac6 antdac7 antdac8 reg_adj0 reg_adj1 0 0 dac9_sw2 dac9_sw iqmix_gain iq_sw fmagc_on amagc_on narrow_off 0 sub-address llll (27) (26) (23) (22) (25) (24) (36) (19) (21) (20) lllllll l lllllllllllllllll ll l lsb msb 00 01 10 11 -23mv (center value) +23mv +64mv 2.7v reg adj 00 01 10 11 standard (gradual) 9bit-dac temperature characteristics compensation slope switching no.a1668-28/40
LV25450PNW fm-rfagc operation 0 1 normal operation fet off fm-keyed-agc operation 0 1 keyed agc normal operation keyed wide agc control function off a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 0 1 1 0 1 0 0 1 1 in3-2 tuner setting 2 address 69h, subaddress [1] in address code sub address code 180 a(2.65v) 245 a(3.3v) s-meter shift(tsout) 00000 00001 00010 00011 00100 00101 00110 00111 11010 11011 11100 11101 11110 11111 0.14v 2.57 fm/am-wide-agc sensitivity 0000 0001 0010 0011 0100 1011 1100 1101 1110 1111 -2db center +2db if agc clamp variations correction 000 001 010 011 100 101 110 111 1.0v 2.5v am-rf-agc amplifier threshold (steep) 0.14v 2.2v fm-keyed agc threshold 0000 0001 0010 0011 0100 1011 1100 1101 1110 1111 0.14v 2.5v fm/am-narrow-agc sensitivity 0000 0001 0010 0011 0100 1011 1100 1101 1110 1111 d32-00 d32-01 d32-02 d32-03 d32-04 d32-05 d32-06 d32-07 d32-08 d32-09 d32-10 d32-11 d32-12 d32-13 d32-14 d32-15 d32-16 d32-17 d32-18 d32-19 d32-20 d32-21 d32-22 d32-23 d32-24 d32-25 d32-26 d32-27 d32-28 d32-29 d32-30 d32-31 w_agc0 w_agc1 w_agc2 w_agc3 n_agc0 n_agc1 n_agc2 n_agc3 1 0 0 0 key_agc0 key_agc1 key_agc2 key_agc3 apf_adj0 apf_adj1 apf_adj2 apf_adj3 s_meter0 s_meter1 s_meter2 s_meter3 s_meter4 adj_n0 adj_n1 adj_n2 0 fmfetoff w_keyed sub-address llll (34)(35) (33) (32) (31) (36) (29) (28) (30) lllllll l lllllllllllllllll ll l lsb msb 1.0 +v be 2.5 +v be [am] rf-agc amp threshold (gradual) small large phase shift trimming 0000 0001 0010 0011 0100 1011 1100 1101 1110 1111 0 1 2 3 4 11 12 13 14 15 [fm] all pass filter steps on the software 0000 1000 0100 1100 0010 1101 0011 1011 0111 1111 no.a1668-29/40
LV25450PNW no.a1668-30/40 control data documentation no. control block/data description related data (1) programmable divider data p0 to p15 dvs ? sets the programmable divider's divisor. this is a binary value in which p0 is the lsb, p15 the msb. dvs = 0 : the ic internal pll in pin is stopped (pulled down) dvs = 1 : the ic internal pll in pin is selected set divisor (n) : 272 to 65536 input frequency range : 120 to 270 mhz * : see the "programmable divider struct ure" section for more information. am/fm osc d1, d2 wb, osc div (2) am oscillator divisor control osc d1, osc d2 ? osc d1, osc d2 ? am oscillator divisor control osc d1 osc d2 divisor 0 0 divide by 10 0 1 divide by 8 1 0 divide by 6 1 1 divide by 4 am/fm p0 to p15 (3) tuner mode switching am/fm ? tuner mode switching between am and fm 1 = am 0 = fm p0 to p15 osc d1, d2 (4) programmable divider stop dvs ? dvs = 0 : the ic internal pll-in pin is stopped (pulled down) dvs = 1 : the ic internal pll-in pin is selected set divisor (n) : 272 to 65536 input frequency range : 120 to 270 mhz * : see the "programmable divider struct ure" section for more information. (5) reference divider data r0 to r3 ? selects the reference frequency. reference frequency setting (khz) r3 r2 r1 r0 crystal : 4.5mhz 0 0 0 0 100 0 0 0 1 50 0 0 1 0 25 0 0 1 1 25 0 1 0 0 12.5 0 1 0 1 6.25 0 1 1 0 3.125 0 1 1 1 3.125 1 0 0 0 10 1 0 0 1 9 1 0 1 0 5 1 0 1 1 1 1 1 0 0 3 1 1 0 1 30 1 1 1 0 illegal value 1 1 1 1 illegal value continued on next page.
LV25450PNW no.a1668-31/40 continued from preceding page. no. control block/data description related data (6) tuner mode switching am/fm oscillator divisor osc_div wb (1) am/fm/wb oscillator divisor control wb osc div divisor 0 0 divide by 2 0 1 divide by 3 1 0 divide by 1 1 1 divide by 1 * : wb: select 1 for weather band reception (2) am oscillator divisor control osd d2 osc d1 divisor 0 0 divide by 10 1 0 divide by 8 0 1 divide by 6 1 1 divide by 4 in fm mode, only the wb and osc div bits are valid. in am mode, this function is set up by combination of the osc d2, osc (however, this is fixed at the divide-by-2 setting) d1, wb, and the osc div bits. fm (japan) : fixed at the divide-by-3 setting fm (other regions) : fixed at the divide-by-2 setting wb : fixed at the divide-by-1 setting (ok if wb = 1) in am mode, set wb = 0, osc div = 0 for the divide-by-2 setting. the osc d2 and osc d1 bits can be set according to end product needs. example : usa : (1) (2) = divide by 20 sw2 : (1) (2) = divide by 8 p0 to p15 dvs (7) fm iq mixer phase adjustment delay_adj0 to delay_adj1 ? fm iq mixer phase adjustment fm-iqmix phase_adjust delay_adj2 delay_adj1 dela y_adj0 adjustment amount 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 small large osc_div continued on next page.
LV25450PNW continued from preceding page. no. control block/data description related data (8) pll filter switching mode fmfil amfil ? switches the pll filter pll filter switching filter state am/fm am filter fm filter 0 off on normal 1 on off normal mode (mode = 0) the filter state is switched in conjunction with the am/fm bit. fm mode (am/fm = 0) a filter is formed on pins 8 and 11. since this filter can be independent of the filt er used in am mode, pll locking can be fast. am mode (am/fm = 1) a filter is formed on pins 9 and 10 and wi th the two internal switches sw1 and sw2. an additional filter is added to pin 5 using an internal resistor and an external capacitor. am/fm (9) ic internal signals i/o ports control data ? specifies the i/o direction for the i/o ports data = 0 : input port. the value 0 should be specified in normal operation. = 1 : output port. a value of 1 is used for ic testing. * : this data must be set to 0 at all times other than ic evaluation. normally set to 0. (10) crystal oscillator oscillation frequency fine adjustment data x_sw_0 to x_sw_2 ? adjusts the crystal 4.5 mhz reference frequency if beating occurs x?tal osc adj [when a 4.5mhz oscillator element is used] 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 high (+100hz) 4.5mhz (center value) low (-100hz) r0 to r3, xlvl0 to xlvl2 3k 1k r7 30k r12 2.2k r11 1.3k c10a 1f c7 0.01f c11a 0.033f c11b 2200pf v dd pin26 cp1 5k sw2 +8v pin61 sw1 sw3 13 12 11 10 9 8 7 fet_gnd vt fm_fet_out am_fet_out am_cp fm_cp continued on next page. no.a1668-32/40
LV25450PNW continued from preceding page. no. control block/data description related data (11) crystal oscillator oscillation level adjustment data xlvl0 to xlvl2 ? data used to adjust the crystal 4.5mhz oscillation level when the s/n condition is worsening. x?tal osc oscillation level adjustment 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 low high r0 to r3, x_sw_0 to x_sw_2 (12) crystal oscillator acl circuit on/off switching alc_off ? switches on and off the alc (auto level control) in the crystal oscillation circuit. normally set to high. alc_on/off switching 0 1 alc_off normal operation (alc_on) (13) do pin control data uld ? determines the do pin output. do pin control data uld do pin 0 low when not locked. 1 open * in such a case that the do pin is multiple xed with eeprom, transmit a setting data that opens the LV25450PNW do pin control just before reading out the eeprom data. the following item (14) must also be set when monitoring the unlock detection signal. ul0, ul1 (14) unlock state detection data ul0, ul1 ? selects the phase error (?e) detection wi dth used to judge the pll locked state. if a phase error in excess of the ?e detection width from the table below occurs, the pll is seen as being in the unlocked state. when the pll is seen as being unlocked, the detection pin (do) is set low. ul1 ul0 e detection width detection pin output 0 0 1 1 0 1 0 1 stopped 0 0.5 s 1 s open e is output directly e is delayed by 1 to 2 ms. e is delayed by 1 to 2 ms. uld delay unlock state output 1 to 2ms do e (15) crystal oscillator buffer output stop switching two_doff ? stops the crystal oscillator buffer output. 1 bit crystal oscillator buffer switching 0 1 normal operation stopped (16) phase comparator control data dz0, dz1 ? controls the phase co mparator's dead zone. dz1 dz0 dead zone mode 0 0 1 1 0 1 0 1 dza dzb dzc dzd the dza setting is selected after the power-on reset. continued on next page. no.a1668-33/40
LV25450PNW no.a1668-34/40 continued from preceding page. no. control block/data description related data (17) charge pump control data dlc ? forcibly sets the charge pump output to the low level (v ss level). dlc = 1 : low level dlc = 0 : normal operation * : if the ic deadlocks with vco oscillator stopped with the vco control voltage (vtune) at 0 v, the deadlock can be resolved by setting th e charge pump output to the low level and setting vtune to v cc . this item is set to the normal operation state after the power-on reset. (18) ic internal signal i/o port control data test0, test1, test2 ? specifies the i/o direction for the i/o ports data = 0 : input port. the value 0 should be specified in normal operation. = 1 : output port. a value of 1 is used for ic testing. * : this data must be set to 0 at all times other than ic evaluation. (19) rf tuning d/a converter output rfdac0 to rfdac8 ? applies a control voltage to the rf tuning circuit (varactor). 9 bit dac9_sw2, dac9_sw (20) tuner off setting tuneroff ? set the ic to tuner off mode. 1 bit tuner off mord 0 1 normal operation tuner-off (21) antenna tuning d/a converter output antdac0 to antdac8 ? applies a control voltage to the antenna tuning circuit (varactor). 9 bit dac9_sw2, dac9_sw (22) 2.7v reg adj reg_adj0 reg_adj1 ? adjusts the 2.7 v regulator 2.7v reg adj 0 0 0 1 1 0 1 1 -23mv (center value) +23mv +64mv (23) rf block tuning circuit temperature characteristics compensatioin slope switching data dac9_sw2 dac9_sw ? rf block tuning circuit temperature charac teristics compensatioin slope switching bits 9bit temperature characteristics compensatioin slope switching 0 0 0 1 1 0 1 1 standard (gradual) rfdac0 to rfdac8, antdac0 to antdac8 (24) iq mixer gain adjustment data iqmix_gain ? data used to switch fm iq mixer gain. 1 bit iq mixer gain adjustment 0 1 gain down (with rf-amp) gain up (without rf-amp) (25) iq mixer phase switching data iq_sw ? data used to switch fm iq mixer phase. 1 bit iq mixer phase switching 0 1 lower upper (26) forced agc (am/fm) switching data fmagc_on amagc_on ? data used to operate the forced agc circuit (antenna dumping). fmagc_on : fm agc ? 0? = normal, ? 1? = on amagc_on : am agc ? 0? = normal, ? 1? = on each 1 bit continued on next page.
LV25450PNW no.a1668-35/40 continued from preceding page. no. control block/data description related data (27) if agc amplifier circuit off switching narrow_off ? switches off the if agc amplifier circuit. 1 bit if agc amplifier 0 1 on (normal operation) off (28) am/fm wide agc setting w_agc0 to w_agc3 ? sets the am/fm wide agc sensitivity. 4 bit am/fm (29) am/fm narrow agc setting n_agc0 to n_agc3 ? sets the am/fm narrow agc sensitivity. 4 bit am/fm (30) am rf agc amplifier threshold (steep) and keyed agc setting data key_agc0 to key_agc3 ? sets the am rf agc amp lifier circuit threshold (steep) and the fm keyed agc sensitivity. 4 bit am-rf-agc fm-keyed amp threshold (steep) agc threshold 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 ? ? 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1.0v 2.5v 0.14v 2.2v am/fm (31) am rf agc amplifier threshold (gradual) and all pass filter setting data apf_adj0 to apf_adj3 ? data used to set the am rf agc amplifier threshold (gradual) and the all pass filter. 4 bit am-rf-agc fm-keyed agc threshold phase shift amp threshold the software trimming (gradual) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 ? ? 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1.0+vbe 2.5v+vbe 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 ? ? 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 2 3 4 ? ? 11 12 13 14 15 small large am/fm (32) s-meter shifter control s_meter0 to s_meter4 ? controls the fm s-meter shifter circuit output value. 5 bit (33) analog (narrow) if agc clamp variations correction adj_n0 to adj_n2 ? corrects the sample-to-sample variations in the if agc clamp circuit. amount of correction : 2 db 3 bit (34) fm pin diode forced on state bit fmfetoff ? forcibly sets the fm pin diode to the on state. 1 bit continued on next page.
LV25450PNW continued from preceding page. no. control block/data description related data (35) lsi test data w_keyed ? modifies the keyed agc connection circuit. 1 bit keyed agc switch 0 1 wide + narroww narrow only (36) sub-address ? sub-code address each 1 bit (37) offset_sw ? the dc offset wa s given to the differential motion part of lo-osc for the irr improvement, and the function to correct duty was added. it is control bit to stop this function, and to switch in a state past (the offset giving is not done). 1bitbit programmable divider structure 4 bits 12 bits programmable divider swallow counter e fvco/n pd ferf fvco = ferf n pll in dvs dvs set divisor (n) input frequency ran ge (f (mhz)) ic internal pll in pin 1 272 to 65535 120 f 270 selected 0 - - stopped * : since the ic is closed internally , the input sensitivity is not specified. no.a1668-36/40
LV25450PNW phase comparator and charge pump circuits (1) phase comparator and charge pump operation in the pll circuit block shown in figure 1, the phase comp arator compares the phases of the reference frequency (fr) and the comparison frequency (fp), and outputs the amo unt of the phase difference from the charge pump. figure 1 pll circuit block reference divider programmable divider phase detector charge pump lpf vco mixer leakage during strong-field input rf fr fp figure 2 shows the phase comparator/charge pump output characteristics. the phase co mparator outputs a voltage v that is proportional to the phase difference between fr and fp. the phase comparator's characteristics can be switched by changing the phase comparator dead zone mode setting. the phase comparator can be set to modes (dza, dzb) in which both the charge pump p-channel and n-channel sides are turned on when the phase difference is small, or can be set to a mode (dzd) that does not output the phase difference when the phase difference is small. figure 2 phase comparator/charge pump characteristics err[ns] v[v] v[v] v[v] v[v] dead zone(--) dza mode dzb mode dzc mode dzd mode err[ns] err[ns] err[ns] dead zone(-) dead zone 0 dead zone(+) fp > fr fp > fr fp > fr fp > fr fr > fp fr > fp fr > fp fr > fp no.a1668-37/40
LV25450PNW no.a1668-38/40 (2) dead zone mode character istics and selection criteria this section describes the characteristics of each dead zone mode and the criteria for selecting that mode. (1) dza mode in dza mode, the correction signal is output from the ch arge pump even if the reference frequency (fr) and comparison frequency (fp) match. this results in excelle nt signal-to-noise ratio characteristics. however, due to the generation of reference frequency component sidebands, beating may occur in the presence of a strong input signal. this is because the pll loop respo nds sensitively to leakage components from the rf stage through the mixer and this modulates the vco. (2) dzb mode like dza mode, in dzb mode the correction signal is output from the charge pump even if the reference frequency (fr) and comparison frequency (fp) match. however, the correction signal voltage is lower in dzb mode than in dza mode. the feature of this mode is that it provides a better signal-to-noise ratio than dzc or dzd mode yet is less susceptible to beating than dza mode. (3) dzc mode in dzc mode, a correction signal proportional to the phase difference between the reference frequency (fr) and comparison frequency (fp) is output from the charge pump. a small amount of noise may occur when the phase difference is close to 0 ns. since the signal-to-noise ratio may degrade significantly at low temperatures (under -30c), this mode should not be used. (4) dzd mode in dzd mode, a correction signal proportional to the phase difference between the reference frequency (fr) and comparison frequency (fp) is output from the charge pump. the correction signal is not output when the phase difference is in the vicinity of . as a result the signal-to-noise ratio is worse than the other modes, but the occurrence of beating is suppressed. power supply turning on/cutting timing and power-on reset recommended operating conditions/ta=25 c, gnd=0v ratings parameter symbol conditions min typ max unit vcop_h pin 3,27,35,54,55,61 7.5 8.5 v operation power-supply voltage vcop_l pin 16,25,41 4.5 5.5 v vreg3 pin 26 2.7 3.3 v internal logic voltage vreg4 pin 15 3.7 4.3 v power supply turning on time(8.0v 5.0v) t7 10 100 ms vhmin3 pin 26 *1 vreg3 2.2 v internal register maintenance voltage vhmin4 pin 15 *1 vreg4 2.2 v internal register reset voltage voff pin 16,25,41 *1 0 0.2 v internal register reset power supply start-up time tpor pin 16,25,41 *1 0.05 3 ms power supply turning on time(5.0v 8.0v) t14 10 100 ms *1: design reference value
LV25450PNW sample application circuit xtal_v cc 5v no.a1668-39/40 64 63 62 61 60 59 58 57 55 56 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 25 27 28 29 30 31 32 280 10.7outn c29 0.022f + + 280 r34 15k r44 1.8k r42 3.9k r42b xtal_16k c45 0.1f c47 0.022f 10.7outp div_out_if div_out_if 10.7m_out_p 10.7m_out_m agc_dac_s c30 0.022f do cl agc_dac_s ifagc_gnd ifagc_v cc b vreg 3v analos-if agc disital v cc ce di ce if_n_in1 if_n_in bypass analog v cc vreg49 if_out address_sw am_nagc am_analog_in vsm_ac vsm_dc am_analog _in bypass analog gnd ifagc driver gnd ifagc driver v cc vreg27 osc_b osc_c fm_fel_in am_fel_in am_cp out fm_cp out vreg 4v disital gnd xtal_v cc xtal_osc xtal_osc out2 fm_in v cc 8v a m_in cl do pull up di v cc d5v ktal_out ktal_in cs if agc_v cc 8v ifagc_driver v cc 8v xtal_gnd snd xtal_dsc am_ant_d rf_agc bypass am_rf_agc am_wagc cf_180k rf_dac ant_dac mix_out2 n_agc mix_out1 am_mix am_mix fm_mix1 fe_v cc 8v fm_mix2 in in in1 in2 fm_antd out2 gnd eeprom test nc v cc 4 3 2 1 5 6 7 8 do di sk cs 30k 47k 30 vcca5v fm amp am amp am 1st amp w agc rf agc n agc ant d + - vreg3 vreg4 in3-1 in1/in2 bus buff cp1 sw r11 r11 2.2k c60 0.1f c51 1f c62 0.022f c53 30pf c49 0.022f r56 30k r62c 180 r57 30k r62 30 coil c54 l72 c62 10pf c63 10pf c1000 8pf vcd2 svc208 c15 0.22f am_filer fet_gnd fet_gnd fm_rf_agc local_osc gnd c8 0.01f c15 0.22f c107 1000pf c63 0.1f c38 1000pf 4.5m c36 0.1f c38 0.022f c34 0.22f c18 15pf c26 0.22f c17 10pf c25 1f c10a 1f c107 0.1f c16a 0.022f c16b 10f c16 0.1f c11a 0.033f r10 1.3k c11b 2200pf 10k 3k +8v c2 2.2f + c58b 0.022f c62c 1000pf c58a 100f + c35a 10f c35b 0.022f c27a 10f c27b 0.022f + + c41a 10f c41b 0.022f + r2 220k c107 1000pf c105 5pf c103 4pf 0.15h c101 18pf 100pf kv1862 pin_d2 1sv251 r635 180 r63m 180 r107a 100k r107b 100k r64 100 r4 30k c5 3pf c4 2pf c48 1pf c45 330pf sw fm osc k agc n agc w agc ant_dac rf_dac ant d rf agc div buff reference counter programable divider phase detecter swallow counter osc buffer in3-2 am mix iq mix vsm vreg49 vreg27 1/12,1/8 1/6,1/4 + fm cut 6.8 h r101g 1m cph5905 c50 10 f 15pf 36pf c101 0.022 f loding coil d70 1sv251 c52 0.022 f c56 1000pf c57 1000pf r52b 470 r49c 220 l49a 1mh l70b 47h r49 470 c61 0.022f
LV25450PNW sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. to change without notice. this catalog provides information as of march, 2010. specifications and information herein are subject ps no.a1668-40/40

▲Up To Search▲

Price & Availability of LV25450PNW

	To Download LV25450PNW Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .